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X96012
Data Sheet February 20, 2008 FN8216.3
Universal Sensor Conditioner with Dual Look-up Table Memory and DACs
The X96012 is a highly integrated bias controller, which incorporates two digitally controlled Programmable Current Generators, temperature compensation with dedicated look-up tables, and supplementary EEPROM array. All functions of the device are controlled via a 2-wire digital serial interface. Two temperature compensated Programmable Current Generators, vary the output current with temperature according to the contents of the associated nonvolatile look-up table. The look-up table may be programmed with arbitrary data by the user, via the 2-wire serial port, and either an internal or external temperature sensor may be used to control the output current response. The integrated General Purpose EEPROM is included for product data storage.
Features
* Two Programmable Current Generators - 3.2mA Max - 8-bit (256 Step) Resolution - Internally Programmable Full Scale Current Outputs - External Resistor Pin to Set Full Scale Current Outputs * Integrated 8-bit A/D Converter * Internal Voltage Reference with Output/Input * Temperature Compensation - Internal or External Sensor - -40C to +100C Range - +2.2C/step Resolution - EEPROM Look-up Tables * Hot Pluggable * 2176-bit EEPROM - 17 Pages - 16 Bytes per Page * Write Protection Circuitry - Intersil BlockLockTM - Logic Controlled Protection - 2-wire Bus with 3 Slave Address Bits * 3V to 5.5V, Single Supply Operation * Package - 14 Ld TSSOP * Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER X96012V14I PART MARKING X9601 2VI TEMP RANGE (C) PACKAGE PKG. DWG. #
-40 to +100 14 Ld TSSOP M14.173 -40 to +100 14 Ld TSSOP M14.173 (Pb-free)
X96012V14IZ* X9601 2VIZ (Note)
*Add "-T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
* PIN Diode Bias Control * RF PA Bias Control
Pinout
X96012 (14 LD TSSOP) TOP VIEW
A0 A1 A2 VCC WP SCL SDA 1 2 3 4 5 6 7 14 I 2 13 VREF 12 VSENSE 11 VSS 10 R2 9 8 R1 I1
* Temperature Compensated Process Control * Laser Diode Bias Control * Fan Control * Motor Control * Sensor Signal Conditioning * Data Aquisition Applications * Gain vs Temperature Control * High Power Audio * Open Loop Temperature Compensation * Closed Loop Current, Voltage, Pressure, Temperature, Speed, Position Programmable Voltage Sources, Electronic Loads, Output Amplifiers or Function Generator
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X96012 Block Diagram
VOLTAGE REFERENCE VREF VSENSE ADC MUX TEMPERATURE SENSOR LOOK-UP TABLE 1 MUX DAC 1 I1 R1 MUX LOOK-UP TABLE 2 MUX DAC 2 R2 I2
CONTROL AND STATUS
SDA SCL WP A2, A1, A0
2-WIRE INTERFACE
GENERAL PURPOSE MEMORY
Pin Descriptions
PIN NUMBER 1 2 3 4 5 PIN NAME A0 A1 A2 VCC WP PIN DESCRIPTION Device Address Select Pin 0. This pin determines the LSB of the device address required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor. Device Address Select Pin 1. This pin determines the intermediate bit of the device address required to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor. Device Address Select Pin 2. This pin determines the MSB of the device address required to communicate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor. Supply Voltage. Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing any "Write" operation. When HIGH, various areas of the memory can be protected using the Block Lock bits BL1 and BL0. The WP pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating. Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output at the SDA pin. Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull-up resistor. Current Generator 1 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. Current Programming Resistor 1. A resistor between this pin and VSS can set the maximum output current available at pin I1. If no resistor is used, the maximum current must be selected using control register bits. Current Programming Resistor 2. A resistor between this pin and VSS can set the maximum output current available at pin I2. If no resistor is used, the maximum current must be selected using control register bits. Ground. Sensor Voltage Input. This voltage input may be used to drive the input of the on-chip A/D converter. Reference Voltage Input or Output. This pin can be configured as either an Input or an Output. As an Input, the voltage at this pin is provided by an external source. As an Output, the voltage at this pin is a buffered output voltage of the on-chip bandgap reference circuit. In both cases, the voltage at this pin is the reference for the A/D converter and the two D/A converters. Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits.
6 7 8 9 10 11 12 13
SCL SDA I1 R1 R2 VSS VSENSE VREF
14
I2
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Absolute Maximum Ratings
All Voltages are Referred to VSS Temperature Under bias . . . . . . . . . . . . . . . . . . . . .-65C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on Every Pin Except VCC. . . . . . . . . . . . . . . . . -1.0V to +7V Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 5.5V DC Output Current at Pin SDA . . . . . . . . . . . . . . . . . . 0mA to 5 mA DC Output Current at Pins R1, R2, VREF and VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50mA to 1mA DC Output Current at Pins I1 and I2 . . . . . . . . . . -3.5mA to +3.5mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +100C Temperature While Writing to Memory . . . . . . . . . . . . 0C to +70C Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V Voltage on any other Pin . . . . . . . . . . . . . . . . . . . . . . . . . VCC 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
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Conditions are as follows, unless otherwise specified. All typical values are for TA = +25C and 5V at pin VCC. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin VSS. All bits in control registers are "0". 255, 0.1%, resistor connected between R1 and VSS, and another between R2 and VSS. 400kHz TTL input at SCL. SDA pulled to VCC through an external 2k resistor. 2-wire interface in "standby" (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating. VREF pin unloaded. TEST CONDITIONS R1 and R2 floating, VREF unloaded. 2-wire interface reading from memory, I1 and I2 both connected to VSS, DAC input bytes: FFh, VREF unloaded. Average from START condition until tWP after the STOP condition WP: VCC, R1 and R2 Floating, VREF unloaded. 0 4 MIN (Note 3) TYP MAX (Note 3) 2 15 UNIT mA mA
SYMBOL Iccstby Iccfull
PARAMETER Stand-by Current into VCC Pin Full Operation Current into VCC Pin Nonvolatile Write Current into VCC Pin
Iccwrite
mA
IPLDN VILTTL VIHTTL IINTTL VOLSDA IOHSDA VILCMOS VIHCMOS VRefout RVREF TCOref VRef Range TSenseRange TSenseAccuracy
On-chip Pull-down Current at WP, V(WP), V(A0), V(A1), and V(A2) from 0V A0, A1, and A2 to VCC SCL and SDA, Input Low Voltage SCL and SDA, Input High Voltage SCL and SDA Input Current SDA Output Low Voltage SDA Output High Current WP, A0, A1, and A2 Input Low Voltage WP, A0, A1, and A2 Input High Voltage Output Voltage at VREF at +25C VREF Pin Input Resistance Temperature Coefficient of VREF Output Voltage Voltage Range when VREF is an Input Temperature Sensor Range Temperature Sensor Accuracy -20A I(VREF) 20A VRM bit = "1", +25C Notes 2 and 8 Note 6 Note 2 Pin voltage between 0 and VCC, and SDA as an input. I(SDA) = 2mA V(SDA) = VCC
1
20 0.8
A V V
2.0 -1 0 0 0 0.8 x VCC 1.205 20 -100 1 -40 +/-2 1.21 10 0.4 100 0.2 x VCC VCC 1.215 40 +100 1.3 100
A V A V V V k ppm/C V C C
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Electrical Specifications
Conditions are as follows, unless otherwise specified. All typical values are for TA = +25C and 5V at pin VCC. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin VSS. All bits in control registers are "0". 255, 0.1%, resistor connected between R1 and VSS, and another between R2 and VSS. 400kHz TTL input at SCL. SDA pulled to VCC through an external 2k resistor. 2-wire interface in "standby" (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating. VREF pin unloaded. (Continued) TEST CONDITIONS MIN (Note 3) 0 1.5 0.2 Figure 11 2.6 TYP MAX (Note 3) 3200 2.8 50 2.8 UNIT A V mV/s V
SYMBOL IR VPOR VCCRamp VADCOK NOTES:
PARAMETER Current from pin R1 or R2 to VSS Power-on Reset Threshold Voltage VCC Ramp Rate ADC Enable Minimum Voltage
2. These parameters are periodically sampled and not 100% tested. 3. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 4. The device goes into Standby: 200ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address Byte. 5. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 6. For this range of V(VREF) the full scale sink mode current at I1 and I2 follows V(VREF) with a linearity error smaller than 1%. 7. These parameters are periodically sampled and not 100% tested. 8. TCOref = [Max V(VREF) - Min V(VREF)] x 106/(1.21V x +140C).
D/A Converter Characteristics (See "Electrical Specifications" table starting on page 3 for standard conditions).
SYMBOL IFS00 PARAMETER TEST CONDITIONS MIN (Note 3) 1.56 TYP 1.58 MAX (Note 3) 1.6 3.2 0.3 0.64 1 1 -2 -0.5 -1 0.4 0.85 1.3 0.5 1.06 1.6 1 2 0.5 1 UNIT mA mA mA mA mA LSB LSB LSB LSB
I1 or I2 Full Scale Current, with External Resistor (Notes 9, 12) Setting (Notes 2, 9, 13) I1 or I2 Full Scale Current, with Internal Low Current Setting Option I1 or I2 Full Scale Current, with Internal Middle Current Setting Option I1 or I2 Full Scale Current, with Internal High Current Setting Option I1 or I2 D/A Converter Offset Error I1 or I2 D/A Converter Full Scale Error I1 or I2 D/A Converter Differential Nonlinearity I1 or I2 D/A Converter Integral Nonlinearity with Respect to a Straight Line Through 0 and the Full Scale Value I1 or I2 Sink Voltage Compliance (Note 12) (Notes 2, 13) DAC input Byte = FFh, Source or sink mode, V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. (Notes 10, 11)
IFS01 IFS10 IFS11 OffsetDAC FSErrorDAC DNLDAC INLDAC
VISink
1.2 2.5 0 0
VCC VCC VCC - 1.2 VCC - 2.5
V V V V
VISource
I1 or I2 Source Voltage Compliance
(Note 12) (Notes 2, 13)
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D/A Converter Characteristics (See "Electrical Specifications" table starting on page 3 for standard conditions). (Continued)
SYMBOL IOVER IUNDER trDAC TCOI1I2 PARAMETER I1 or I2 Overshoot on D/A Converter Data Byte Transition I1 or I2 Undershoot on D/A Converter Data Byte Transition I1 or I2 Rise Time on D/A Converter Data Byte Transition; 10% to 90% Temperature Coefficient of Output Current I1 or I2 when Using Internal Resistor Setting Bits I1FSO[1:0] | 002 or Bits I2FSO[1:0] | 002, VRMbit = "1" See Figure 8 TEST CONDITIONS DAC input byte changing from 00h to FFh and vice versa, V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. (Note 2) 5 200 MIN (Note 3) TYP MAX (Note 3) 0 0 30 UNIT A A s ppm/C
NOTES: 10. LSB is defined as 9. DAC input Byte = FFh, Source or sink mode. 2 V(VRef) divided by the resistance between R1 or R2 to VSS. x 255 3 11. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
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12. V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%. 13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
.
A/D Converter Characteristics (See "Electrical Specifications" table starting on page 3 for standard conditions).
SYMBOL ADCTIME PARAMETER A/D Converter Conversion Time TEST CONDITIONS Proportional to A/D converter input voltage. This value is maximum at full scale input of A/D converter. ADCfiltOff = "1" VSense as an input, ADCIN bit = "1" VSense as an input, ADCIN bit = "1", Frequency = 1 MHz. (Note 2) This is the A/D Converter Dynamic Range. ADCIN bit = "1" 100 1 0 7 V(VRef) MIN (Note 3) TYP MAX (Note 3) 9 UNIT ms
RINADC CINADC VINADC
VSense Pin Input Resistance VSense Pin Input Capacitance VSense Input Signal Range
k pF V
THE ADC IS MONOTONIC OffsetADC FSErrorADC DNLADC INLADC TempStepADC Out25ADC A/D Converter Offset Error A/D Converter Full Scale Error A/D Converter Differential Nonlinearity A/D Converter Integral Nonlinearity Temperature Step Causing One Step Increment of ADC Output ADC Output at +25C (Note 2) 0.52 (Notes 2, 14) 1 1 0.5 1 0.55 011101012 0.58 LSB LSB LSB LSB C
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A/D Converter Characteristics (See "Electrical Specifications" table starting on page 3 for standard conditions).
SYMBOL NOTES: 14. LSB" is defined as V(VRef)/255, "Full-Scale" is defined as V(VRef). 0.5 x V(VRef) above zero. Offset error is the amount of 15. OffsetADC: For an ideal converter, the first transition of its transfer curve occurs at 255 deviation between the measured first transition point and the ideal point. FSErrorADC: For an ideal converter, the last transition of its transfer 254.5 x V(VRef) curve occurs at . Full-Scale Error is the amount of deviation between the measured last transition point and the ideal point, 255 after subtracting the Offset from the measured curve. DNLADC: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Full-scale errors before calculating DNL. INLADC: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer curve is adjusted for Offset and Full scale errors before calculating INL. PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT
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2-Wire Interface AC Characteristics
SYMBOL fSCL tIN (Note 2) tAA (Note 2) tBUF (Note 2) tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR (Note 2) tF (Note 2) tSU:WP (Note 2) tHD:WP (Note 2) Cb (Note 2) PARAMETER SCL Clock Frequency Pulse width Suppression Time at Inputs SCL Low to SDA Data Out Valid Time the Bus Free Before Start of New Transmission Clock Low Time Clock High Time Start Condition Set-up Time Start Condition Hold Time Data In Set-up Time Data In Hold Time Stop Condition Set-up Time Data Output Hold Time SDA and SCL Rise Time SDA and SCL Fall Time WP Set-up Time WP Hold Time Capacitive Load for Each Bus Line 1300 1.3 0.6 600 600 100 0 600 50 20 +0.1Cb (Note 16) 20 +0.1Cb (Note 16) 600 600 400 300 300 1200 (Note 18) 1200 (Note 18) TEST CONDITIONS See "2-Wire Interface Test Conditions" on page 6 See Figures 1, 2, 3. MIN (Note 3) 1 (Note 18) TYP MAX (Note 3) 400 50 900 UNITS kHz ns ns ns s s ns ns ns s ns ns ns ns ns ns pF
2-Wire Interface Test Conditions
Input Pulse Levels Input Rise and Fall Times, between 10% and 90% Input and Output Timing Threshold Level External Load at Pin SDA 10% to 90% of VCC 10ns 1.4V 2.3k to VCC and 100pF to VSS
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Nonvolatile WRITE Cycle Timing
SYMBOL tWC (Note 17) NOTES: 16. Cb = total capacitance of one bus line (SDA or SCL) in pF. 17. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 18. The minimum frequency requirement applies between a START and a STOP condition. PARAMETER Nonvolatile Write Cycle Time TEST CONDITIONS See Figure 3 MIN (Note 3) TYP 5 MAX (Note 3) 10 UNITS ms
Timing Diagrams
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA IN
tSU:DAT tHD:DAT tSU:STO
tAA SDA OUT
tDH
tBUF
FIGURE 1. BUS TIMING
START
STOP
SCL
CLK 1
SDA IN tSU:WP WP tHD:WP
FIGURE 2. WP PIN TIMING
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SCL
SDA
8TH BIT OF LAST BYTE
ACK tWC STOP CONDITION START CONDITION
FIGURE 3. NON-VOLATILE WRITE CYCLE TIMING
Intersil Sensor Conditioner Product Family
FSO = Full Scale Output, Ext = External, Int = Internal. FEATURES/FUNCTIONS FSO CURRENT DAC SETTING RESISTORS Ext
DEVICE
TITLE
EXTERNAL INTERNAL INTERNAL VOLTAGE SENSOR TEMPERATURE REFERENCE INPUT SENSOR No Yes Yes
VREF I/O Yes
GENERAL PURPOSE EEPROM No
LOOK-UP TABLE ORGANIZATION Dual Bank
# OF DACS Dual
X96010 Sensor Conditioner with Dual Look-Up Table Memory and DACs X96011 Temperature Sensor with Look-Up Table Memory and DAC X96012 Universal Sensor Conditioner with Dual Look-Up Table Memory and DACs
Yes
No
Yes
No
No
Single Bank
Single
Int
Yes
Yes
Yes
Yes
Yes
Dual Bank
Dual
Ext/Int
Device Description
The X96012 combines two Programmable Current Generators, and integrated EEPROM with Block LockTM protection in one package. The combination of the X96012 functionality and Intersil's QFN package lowers system cost, increases reliability, and reduces board space requirements. Two on-chip Programmable Current Generators may be independently programmed to either sink or source current. The maximum current generated is determined by using an externally connected programming resistor, or by selecting one of three predefined values. Both current generators have a maximum output of 3.2mA, and may be controlled to an absolute resolution of 0.39% (256 steps/8-bit). Both current generators may be driven using an on-board temperature sensor, an external sensor, or Control Registers. The internal temperature sensor operates over a very broad temperature range (-40C to +100C). The
sensor output (internal or external) drives an 8-bit A/D converter. The six MSBs of the ADC output select one of 64 bytes from each nonvolatile look-up table (LUT). The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which generates the output current. All control and set-up parameters of the X96012, including the look-up tables, are programmable via the 2-wire serial port. The general purpose memory portion of the device is a CMOS serial EEPROM array with Intersil's Block LockTM protection. The EEPROM array is internally organized as 272x8 bits with 16-Byte pages, and utilizes Intersil's proprietary Direct WriteTM cells, providing a minimum endurance of 100,000 Page Write cycles and a minimum data retention of 100 years.
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X96012 Principles of Operation
Control and Status Registers
The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96012. The X96012 contains seven Control, one Status, and several Reserved registers, each being one Byte wide. (Figure 4). The Control registers 0 through 6 are located at memory addresses 80h through 86h respectively. The Status register is at memory address 87h, and the Reserved registers at memory address 88h through 8Fh. All bits in Control register 6 always power-up to the logic state "0". All bits in Control registers 0 through 5 power-up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a register retain their stored values even when the X96012 is powered down, then powered back up. The nonvolatile bits in Control 0 through Control 5 registers are all preprogrammed to the logic state "0" at the factory. Bits indicated as "Reserved" are ignored when read, and must be written as "0", if any Write operation is performed to their registers. A detailed description of the function of each of the Control and Status register bits follows: VRM: VOLTAGE REFERENCE PIN MODE (NON-VOLATILE) The VRM bit configures the Voltage Reference pin (VREF) as either an input or an output. When the VRM bit is set to "0" (default), the voltage at pin VREF is an output from the X96012's internal voltage reference. When the VRM bit is set to "1", the voltage reference for the VREF pin is external. See Figure 5. ADCIN: A/D CONVERTER INPUT SELECT (NON-VOLATILE) The ADCIN bit selects the input of the on-chip A/D converter. When the ADCIN bit is set to "0" (default), the output of the on-chip temperature sensor is the input to the A/D converter. When the ADCIN bit is set to "1", the input to the A/D converter is the voltage at the VSENSE pin. See Figure 7. ADCFILTOFF: ADC FILTERING CONTROL (NON-VOLATILE) When this bit is "1", the status register at 87h is updated after every conversion of the ADC. When this bit is "0" (default), the status register is updated after four consecutive conversions with the same result, on the 6 MSBs. NV1234: CONTROL REGISTERS 1, 2, 3 AND 4 VOLATILITY MODE SELECTION BIT (NON-VOLATILE) When the NV1234 bit is set to "0" (default), bytes written to Control registers 1, 2, 3, and 4 are stored in volatile cells, and their content is lost when the X96012 is powered down. When the NV1234 bit is set to "1", bytes written to Control registers 1, 2, 3, and 4 are stored in both volatile and nonvolatile cells, and their value doesn't change when the X96012 is powered down and powered back up. See "Writing to Control Registers" on page 20. I1DS: CURRENT GENERATOR 1 DIRECTION SELECT BIT (NON-VOLATILE) The I1DS bit sets the polarity of Current Generator 1, DAC1. When this bit is set to "0" (default), the Current Generator 1 of the X96012 is configured as a Current Source. Current Generator 1 is configured as a Current Sink when the I1DS bit is set to "1". See Figure 8. I2DS: CURRENT GENERATOR 2 DIRECTION SELECT BIT (NON-VOLATILE) The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to "0" (default), the Current Generator 2 of the X96012 is configured as a Current Source. Current Generator 2 is configured as a Current Sink when the I2DS bit is set to "1". See Figure 8.
Control Register 0
This register is accessed by performing a Read or Write operation to address 80h of memory. BL1, BL0: BLOCK LOCK PROTECTION BITS (NON-VOLATILE) These two bits are used to inhibit any write operation to certain addresses within the memory array. The protected region of memory is determined by the values of the two bits, as shown in Table 1.
TABLE 1. PROTECTED ADDRESSES (SIZE) None (Default) 00h to 7Fh (128 bytes) 00h to 7Fh and 90h to CFh (192 bytes) 00h to 7Fh and 90h to 10Fh (256 bytes) PARTITION OF ARRAY LOCKED None (Default) GPM GPM, LUT1 GPM, LUT1, LUT2 BL1 0 0 1 1 BL0 0 1 0 1
If the user attempts to perform a write operation to a protected region of memory, the operation is aborted without changing any data in the array. Notice that if the Write Protect (WP) input pin of the X96012 is active (LOW), then any write operation to the memory is inhibited, irrespective of the Block Lock bit settings.
Control Register 1
This register is accessed by performing a Read or Write operation to address 81h of memory. This byte's volatility is determined by bit NV1234 in Control register 0.
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L1DA5 - L1DA0: LUT1 DIRECT ACCESS BITS When bit L1DAS (bit 4 in Control register 5) is set to "1", LUT1 is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit L1DAS is set to "0", these six bits are ignored by the X96012. See Figure 10. A value between 00h (0010) and 3Fh (6310) may be written to these register bits, to select the corresponding row in LUT1. The written value is added to the base address of LUT1 (90h).
Control Register 2
This register is accessed by performing a read or write operation to address 82h of memory. This byte's volatility is determined by bit NV1234 in Control register 0. L2DA5 - L2DA0: LUT2 DIRECT ACCESS BITS When bit L2DAS (bit 6 in Control register 5) is set to "1", LUT2 is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit L2DAS is set to "0", these six bits are ignored by the X96012. See Figure 10. A value between 00h (0010) and 3Fh (6310) may be written to these register bits, to select the corresponding row in LUT2. The written value is added to the base address of LUT2 (D0h).
Control Register 3
This register is accessed by performing a Read or Write operation to address 83h of memory. This byte's volatility is determined by bit NV1234 in Control register 0. D1DA7 - D1DA0: D/A 1 DIRECT ACCESS BITS When bit D1DAS (bit 5 in Control register 5) is set to "1", the input to the D/A converter 1 is the content of bits D1DA7 D1DA0, and it is not a row of LUT1. When bit D1DAS is set to "0" (default) these eight bits are ignored by the X96012. See Figure 9.
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BYTE ADDRESS MSB 7 6 5 4 3 2 1 LSB 0 REGISTER NAME
80h NON-VOLATILE
I2DS
I1DS
NV1234 CONTROL 1, 2, 3, 4 VOLATILITY 0: VOLATILE 1: NONVOLATILE
ADCfiltOff ADC FILTERING 0: ON 1: OFF
ADCIN
VRM
BL1
BL0
CONTROL 0
I1 AND I2 DIRECTION 0: SOURCE 1: SINK
ADC INPUT VOLTAGE 0: INTERNAL REFERENCE 1: EXTERNALMODE 0: INTERNAL 1: EXTERNAL
BLOCK LOCK 00: NONE LOCKED 01: GPM LOCKED 10: GPM, LUT1, LOCKED 11: GPM, LUT1, LUT2 LOCKED
DIRECT ACCESS TO LUT1 81h VOLATILE OR NON-VOLATILE RESERVED RESERVED L1DA5 L1DA4 L1DA3 L1DA2 L1DA1 L1DA0 CONTROL 1
DIRECT ACCESS TO LUT2 82h VOLATILE OR NON-VOLATILE RESERVED RESERVED L2DA5 L2DA4 L2DA3 L2DA2 L2DA1 L2DA0 CONTROL 2
DIRECT ACCESS TO DAC1 83h VOLATILE OR NON-VOLATILE D1DA7 D1DA6 D1DA5 D1DA4 D1DA3 D1DA2 D1DA1 D1DA0 CONTROL 3
DIRECT ACCESS TO DAC2 84h VOLATILE OR NON-VOLATILE D2DA7 D2DA6 D2DA5 D2DA4 D2DA3 D2DA2 D2DA1 D2DA0 CONTROL 4
85h NON-VOLATILE
D2DAS DIRECT ACCESS TO DAC2 0: DISABLED 1: ENABLED
L2DAS
D1DAS
L1DAS
I2FSO1
I2FSO0
I1FSO1
I1FSO0
CONTROL 5
DIRECT DIRECT DIRECT ACCESS ACCESS ACCESS TO LUT2 TO DAC1 TO LUT1 0: DISABLED 0: DISABLED 0: DISABLED 1: ENABLED 1: ENABLED 1: ENABLED
R2 SELECTION 00: EXTERNAL 01: LOW INTERNAL 10: MIDDLE INTERNAL 11: HIGH INTERNAL
R1 SELECTION 00: EXTERNAL 01: LOW INTERNAL 10: MIDDLE INTERNAL 11: HIGH INTERNAL
86h VOLATILE
WEL WRITE ENABLE LATCH 0: WRITE DISABLED 1: WRITE ENABLED ADC OUTPUT
RESERVED
RESERVED RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CONTROL 6
87h VOLATILE
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
STATUS
REGISTERS IN BYTE ADDRESSES 88h THROUGH 8Fh ARE RESERVED.
FIGURE 4. CONTROL AND STATUS REGISTER FORMAT
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X96012
Control Register 4
This register is accessed by performing a Read or Write operation to address 84h of memory. This byte's volatility is determined by bit NV1234 in Control register 0. D2DA7 - D2DA0: D/A 2 DIRECT ACCESS BITS When bit D2DAS (bit 7 in Control register 5) is set to "1", the input to the D/A converter 1 is the content of bits D2DA-D2DA0, and it is not a row of LUT2. When bit D2DAS is set to "0" (default) these eight bits are ignored by the X96012. See Figure 9. L1DAS: LUT1 DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit L1DAS is set to "0" (default), LUT1 is addressed by the output of the on-chip A/D converter. When bit L1DAS is set to "1", LUT1 is addressed by bits L1DA5 - L1DA0. D1DAS: D/A 1 DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit D1DAS is set to "0" (default), the input to the D/A converter 1 is a row of LUT1. When bit D1DAS is set to "1", that input is the content of the Control register 3. L2DAS: LUT2 DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit L2DAS is set to "0" (default), LUT2 is addressed by the output of the on-chip A/D converter. When bit L2DAS is set to "1", LUT2 is addressed by bits L2DA5 - L2DA0. D2DAS: D/A 2 DIRECT ACCESS SELECT BIT (NONVOLATILE) When bit D2DAS is set to "0" (default), the input to the D/A converter 2 is a row of LUT2. When bit D2DAS is set to "1", that input is the content of the Control register 4.
Control Register 5
This register is accessed by performing a Read or Write operation to address 85h of memory. I1FSO1 - I1FSO0: CURRENT GENERATOR 1 FULL SCALE OUTPUT SET BITS (NON-VOLATILE) These two bits are used to set the full scale output current at the Current Generator 1 pin, I1. If both bits are set to "0" (default), an external resistor connected between pin R1 and VSS, determines the full scale output current available at pin I1. The other three options are indicated in Table 2. The direction of this current is set by bit I1DS in Control register 0. See Figure 8.
TABLE 2. I1FSO1 0 0 1 1 I1FSO0 0 1 0 1 I1 FULL SCALE OUTPUT CURRENT Set externally via pin R1 (Default) 0.4mA* 0.85mA* 1.3mA*
Control Register 6
This register is accessed by performing a Read or Write operation to address 86h of memory. WEL: WRITE ENABLE LATCH (VOLATILE) The WEL bit controls the Write Enable status of the entire X96012 device. This bit must be set to "1" before any other Write operation (volatile or nonvolatile). Otherwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. The WEL bit is a volatile latch that powers up in the "0" state (disabled). The WEL bit is enabled by writing 100000002 to Control register 6. Once enabled, the WEL bit remains set to "1" until the X96012 is powered down, and then up again, or until it is reset to "0" by writing 000000002 to Control register 6. A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control register 6.
NOTE: *No external resistor should be connected in these cases between R1 and VSS.
I2FSO1 - I2FSO0: CURRENT GENERATOR 2 FULL SCALE OUTPUT CURRENT SET BITS (NON-VOLATILE) These two bits are used to set the full scale output current at the Current Generator 2 pin, I2. If both bits are set to "0" (default), an external resistor connected between pin R2 and Vss, determines the full scale output current available at pin I2. The other three options are indicated Table 3. The direction of this current is set by bit I2DS in Control Register 0.
TABLE 3. I2FSO1 0 0 1 1 I2FSO2 0 1 0 1 I2 FULL SCALE OUTPUT CURRENT Set externally via pin R2 (Default) 0.4mA* 0.85mA* 1.3mA*
Status Register - ADC Output
This register is accessed by performing a Read operation to address 87h of memory. AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ ONLY) These eight bits are the binary output of the on-chip A/D converter. The output is 000000002 for minimum input and 111111112 for full scale input. The six MSBs select a row of the LUTs.
NOTE: *No external resistor should be connected in these cases between R2 and VSS.
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X96012 Voltage Reference
The voltage reference to the A/D and D/A converters on the X96012, may be driven from the on-chip voltage reference, or from an external source via the VREF pin. Bit VRM in Control Register 0 selects between the two options. See Figure 5. The default value of VRM is "0", which selects the internal reference. When the internal reference is selected, it's output voltage is also an output at pin VREF with a nominal value of 1.21 V. If an external voltage reference is preferred, the VRM bit of the Control Register 0 must be set to "1".
VRM: BIT 2 IN CONTROL REGISTER 0
The A/D converter input voltage range (VINADC) is from 0V to V(VREF).
A/D Converter Input Select
The input signal to the A/D converter on the X96012, may be the output of the on-chip temperature sensor, or an external source via the VSENSE pin. Bit ADCIN in Control register 0 selects between the two options. See Figure 7. It's default value is "0", which selects the internal temperature sensor. If an external source is intended as the input to the A/D converter, the ADCIN bit of the Control register 0 must be set to "1".
A/D Converter Range
ADCIN: BIT 3 IN CONTROL REGISTER 0.
VREF PIN
ON-CHIP VOLTAGE REFERENCE A/D CONVERTER AND D/A CONVERTERS REFERENCE
VSENSE PIN ON-CHIP TEMPERATURE SENSOR
TO A/D CONVERTER INPUT
FIGURE 5. VOLTAGE REFERENCE STRUCTURE
A/D Converter
The X96012 contains a general purpose, on-chip, 8-bit Analog to Digital (A/D) converter whose output is available at the Status Register as bits AD[7:0]. By default these output bits are used to select a row in the look-up tables associated with the X96012's Current Generators. When bit ADCfiltOff is "0" (default), bits AD[7:0] are updated each time the ADC performs four consecutive conversions with the same exact result at the 6 MSBs. When bit ADCfiltOff is "1", these bits are updated after every ADC conversion. A block diagram of the A/D converter is shown in Figure 6. The voltage reference input (see "Voltage Reference" on page 13), sets the maximum amplitude of the ramp generator output. The A/D converter input signal (see "A/D Converter Input Select" on page 13 for details) is compared to the ramp generator output. The control and encode logic produces a binary encoded output, with a minimum value of 00h (010), and a full scale output value of FFh (25510).
VREF
FIGURE 7. A/D CONVERTER INPUT SELECT STRUCTURE
From Figure 6 we can see that the operating range of the A/D converter input depends on the voltage reference. And from Figure 7 we see that the internal temperature Sensor output also varies with the voltage reference (VREF). Table 4 summarizes the voltage range restrictions on the VSENSE and VREF pins in different configurations.
TABLE 4. VSENSE AND VREF RANGES VREF Internal Internal External External A/D CONVERTER INPUT Internal Temp Sensor VSense Pin VSense Pin Internal Temp. Sensor RANGES Not Applicable 0 V(VSense) V(VREF) 0 V(VREF) 1.3 V 0 V(VSense) V(VREF) Not a Valid Case
All voltages referred to VSS
COMPARATOR A/D CONVERTER INPUT CONTROL AND ENCODE LOGIC FROM VREF RAMP GENERATOR CONVERSION RESET 8 A/D CONVERTER OUTPUT (TO LUTS AND STATUS REGISTER)
CLOCK
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X96012 Look-Up Tables
The X96012 memory array contains two 64-byte look-up tables. One is associated to pin I1's output current generator and the other to pin I2's output current generator, through their corresponding D/A converters. The output of each look-up table is the byte contained in the selected row. By default these bytes are the inputs to the D/A converters driving pins I1 and I2. The byte address of the selected row is obtained by adding the look-up table base address (90h for LUT1, and D0h for LUT2) and the appropriate row selection bits. See Figure 9. By default, the look-up table selection bits are the 6 MSBs of the A/D converter output. Alternatively, the A/D converter can be bypassed and the six row selection bits are the six LSBs of Control Registers 1 and 2, for the LUT1 and LUT2 respectively. The selection between these options is illustrated in Figure 10, and described in "I2DS: Current Generator 2 Direction Select Bit (Non-volatile)" on page 9, and "Control Register 2" on page 10.
Current Generator Block
The Current Generator pins I1 and I2 are outputs of two independent current mode D/A converters.
D/A Converter Operation
The Block Diagram for each of the D/A converters is shown in Figure 8. The input byte of the D/A converter selects a voltage on the non-inverting input of an operational amplifier. The output of the amplifier drives the gate of a FET, whose source is connected to ground via resistor R1 or R2. This node is also fed back to the inverting input of the amplifier. The drain of the FET is connected to the output current pin (I1 or I2) via a "polarity select" circuit block.
VCC
I1DS OR I2DS: BITS 6 OR 7 IN CONTROL REGISTER 0.
POLARITY SELECT CIRCUIT
I1 OR I2 PIN
VREF DAC1 OR DAC2 INPUT BYTE
VOLTAGE DIVIDER
+ R1 OR R2 PIN
R1_HIGH_CURRENT OR R2_HIGH_CURRENT
R1_MIDDLE_CURRENT OR R2_MIDDLE_CURRENT
I1FSO[1:0] OR I2FSO[1:0] BITS 1 AND 0, OR 3 AND 2 IN CONTROL REGISTER 5
11 10
00 01 R1_LOW_CURRENT OR R2_LOW_CURRENT
R1_EXTERNAL OR R2_EXTERNAL OPTIONAL EXTERNAL RESISTOR
VSS
VSS
VSS
VSS
FIGURE 8. D/A CONVERTER BLOCK DIAGRAM
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X96012
D2DA[7:0] : CONTROL REGISTER 4 LUT2 LUT2 ROW SELECTION BITS 6 A D D E R 8 ... 10FH 8 8 D1 D0 OUT SELECT D0H D2DAS: BIT 7 OF CONTROL REGISTER 5 DAC 2 INPUT BYTE
D0H
8
D1DA[7:0] : CONTROL REGISTER 3 LUT1 LUT1 ROW SELECTION BITS 6 A D D E R 8 ... CFH 8 8 D1 D0 OUT SELECT 90H D1DAS: BIT 5 OF CONTROL REGISTER 5 DAC 1 INPUT BYTE
90H
8
FIGURE 9. LOOK-UP TABLE (LUT) OPERATION
By examining the block diagram in Figure 8, we see that the maximum current through pin I1 is set by fixing values for V(VREF) and R1. The output current can then be varied by changing the data byte at the D/A converter input. In general, the magnitude of the current at the D/A converter output pins (I1, I2) may be calculated using Equation 1:
Ix = ( V * ( Vref ) ( 384 * Rx ) ) * N (EQ. 1)
D/A Converter Output Current Response
When the D/A converter input data byte changes by an arbitrary number of bits, the output current changes from an initial current level (Ix) to some final level (Ix + Ix). The transition is monotonic and glitchless.
D/A Converter Control
The data byte inputs of the D/A converters can be controlled in three ways: 1) With the A/D converter and through the look-up tables (default), 2) Bypassing the A/D converter and directly accessing the look-up tables, 3) Bypassing both the A/D converter and look-up tables, and directly setting the D/A converter input byte. The options are summarized in Tables 5 and 6.
TABLE 5. D/A CONVERTER 1 ACCESS SUMMARY L1DAS 0 1 X D1DAS 0 0 1 CONTROL SOURCE A/D converter through LUT1 (Default) Bits L1DA5 - L1DA0 through LUT1 Bits D1DA7 - D1DA0
where x = 1, 2 and N is the decimal representation of the input byte to the corresponding D/A converter. The value for the resistor Rx (x = 1, 2) determines the full scale output current that the D/A converter may sink or source. The full scale output current has a maximum value of 3.2mA, which is obtained using a resistance of 255 for Rx. This resistance may be connected externally to pin Rx of the X96012, or may be selected from one of three internal values. Bits I1FSO1 and I1FSO0 select the full scale output current setting for I1 as described in "I1FSO1 - I1FSO0: Current Generator 1 Full Scale Output Set Bits (Non-volatile)" on page 12. Bits I2FSO1 and I2FSO0 select the maximum current setting for I2. When an internal resistor is selected for R1 or R2, then no resistor should be connected externally at the corresponding pin. Bits I1DS and I2DS in Control Register 0 select the direction of the currents through pins I1 and I2 independently (see "I1DS: Current Generator 1 Direction Select Bit (Non-volatile)" on page 9 and "Control and Status Registers" on page 9).
NOTE: "X" = Don't Care Condition (May be either "1" or "0") TABLE 6. D/A CONVERTER 2 ACCESS SUMMARY L2DAS 0 1 X D2DAS 0 0 1 CONTROL SOURCE A/D converter through LUT2 (Default) Bits L2DA5 - L2DA0 through LUT2 Bits D2DA7 - D2DA0
NOTE: "X" = Don't Care Condition (May be either "1" or "0")
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X96012
VOLTAGE VCC VADCOK
0V
TIME
CURRENT IX
ADC TIME
IX X 10%
TIME
FIGURE 11. D/A CONVERTER POWER-ON RESET RESPONSE
VOLTAGE REFERENCE
L2DA[5:0]: CONTROL REGISTER 2
D1 OUT D0 SELECT
LUT2 ROW SELECTION BITS
VOLTAGE INPUT
ADC 8
6
L2DAS: BIT 6 IN CONTROL REGISTER 5 L1DA[5:0]: CONTROL REGISTER 1 6
AD[7:0] STATUS REGISTER
D1 OUT D0 SELECT
LUT1 ROW SELECTION BITS
L1DAS: BIT 4 IN CONTROL REGISTER 5
FIGURE 10. LOOK-UP TABLE ADDRESSING
The A/D converter is shared between the two current generators but the look-up tables, D/A converters, control bits, and selection bits can be set completely independently. Bits D1DAS and D2DAS are used to bypass the A/D converter and look-up tables, allowing direct access to the inputs of the D/A converters with the bytes in control registers 3 and 4 respectively. See Figure 9 and the descriptions of the control bits starting on page 9. Bits I1DS and I2DS in Control Register 0 select the direction of the currents through pins I1 and I2 independently See Figure 8 and the descriptions of the control bits starting on page 9.
Power-on Reset
When power is applied to the VCC pin of the X96012, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at VCC becomes larger than the power-on reset threshold voltage (VPOR), the device recalls all control bits from non-volatile memory into volatile registers. Next, the analog circuits are powered up. When the voltage at Vcc becomes larger than a second voltage threshold (VADCOK), the ADC is enabled. In the default case, after the ADC performs four consecutive conversions with the same exact result, the ADC output is used to select a byte from each look-up table. Those bytes become the input of the DACs.
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X96012
During all the previous sequence the input of both DACs are 00h. If bit ADCfiltOff is "1", only one ADC conversion is necessary. Bits D1DAS, D2DAS, L1DAS, and L2DAS, also modify the way the two DACs are accessed the first time after power-up, as described in "Control Register 5" on page 12. The X96012 is a hot pluggable device. Voltage disturbances on the VCC pin are handled by the power-on reset circuit, allowing proper operation during hot plug-in applications.
Serial Stop Condition
All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 12.
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 14. The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 1010, and the Device Address bits matching the logic state of pins A2, A1, and A0. See Figure16. If a write operation is selected, the device responds with an ACK after the receipt of each subsequent 8-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. The X96012 acknowledges all incoming data and address bytes except: 1) The "Slave Address Byte" when the "Device Identifier" or "Device Address" are wrong; 2) All "Data Bytes" when the "WEL" bit is "0", with the exception of a "Data Byte" addresses to location 86h; 3) "Data Bytes" following a "Data Byte" addressed to locations 80h, 85h, or 86h.
Serial Interface
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X96012 operates as a slave in all applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 13. On power-up of the X96012, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 12.
SCL
SDA
START
STOP
FIGURE 12. VALID START AND STOP CONDITIONS
SCL
SDA DATA STABLE DATA CHANGE DATA STABLE
FIGURE 13. VALID DATA CHANGES ON THE SDA BUS
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X96012
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
SDA OUTPUT FROM RECEIVER START ACK
FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER
X96012 Memory Map
The X96012 contains a 2176 bit array of mixed volatile and nonvolatile memory. This array is split up into four distinct parts, namely: (Refer to Figure 15). * General Purpose Memory (GPM) * Look-up Table 1 (LUT1) * Look-up Table 2 (LUT2) * Control and Status Registers The GPM is all nonvolatile EEPROM, located at memory addresses 00h to 7Fh.
ADDRESS 10FH FFH D0H CFH 90H 8FH 80H 7FH GENERAL PURPOSE MEMORY (GPM) 00H 7 0 128 BYTES CONTROL AND STATUS REGISTERS 16 BYTES LOOK-UP TABLE 1 (LUT1) 64 BYTES LOOK-UP TABLE 2 (LUT2) 64 BYTES SIZE
Both look-up tables LUT1 and LUT2 are realized as non-volatile EEPROM, and extend from memory locations 90h - CFh and D0h - 10Fh respectively. These look-up tables are dedicated to storing data solely for the purpose of setting the outputs of Current Generators I1 and I2 respectively. All bits in both look-up tables are preprogrammed to "0" at the factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a START, followed by a Slave Address Byte. The Slave address selects the X96012, and specifies if a Read or Write operation is to be performed. It should be noted that the Write Enable Latch (WEL) bit must first be set in order to perform a Write operation to any other bit. See "WEL: Write Enable Latch (Volatile)" on page 12. Also, all communication to the X96012 over the 2-wire serial bus is conducted by sending the MSB of each byte of data first. Even though the 2176 bit memory consists of four differing functions, it is physically realized as one contiguous array, organized as 17 pages of 16 bytes each. The X96012 2-wire protocol provides one address byte, therefore, only 256 bytes can be addressed directly. The next few sections explain how to access the different areas for reading and writing.
SA7 1 SA6 0 SA5 1 SA4 0 SA3 AS2 SA2 AS1 SA1 AS0 SA0 R/W
FIGURE 15. X96012 MEMORY MAP
The Control and Status registers of the X96012 are used in the test and setup of the device in a system. These registers are realized as a combination of both volatile and nonvolatile memory. These registers reside in the memory locations 80h through 8Fh. The reserved bits within registers 80h through 86h, must be written as "0" if writing to them, and should be ignored when reading. The reserved registers, from 88h through 8Fh, must not be written, and their content should be ignored.
DEVICE TYPE IDENTIFIER
DEVICE ADDRESS
READ OR WRITE
SLAVE ADDRESS BIT(S) SA7 - SA4 SA3 - SA1 SA0
DESCRIPTION Device Type Identifier Device Address Read or Write Operation Select
FIGURE 16. SLAVE ADDRESS (SA) FORMAT
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X96012
Slave Address Byte
Following a START condition, the master must output a Slave Address Byte. Refer to Figure 16. This byte includes three parts: * The four MSBs (SA7 - SA4) are the Device Type Identifier, which must always be set to 1010 in order to select the X96012. * The next three bits (SA3 - SA1) are the Device Address bits (AS2 - AS0). To access any part of the X96012's memory, the value of bits AS2, AS1, and AS0 must correspond to the logic levels at pins A2, A1, and A0 respectively. * The LSB (SA0) is the R/W bit. This bit defines the operation to be performed on the device being addressed. When the R/W bit is "1", then a Read operation is selected. A "0" selects a Write operation (refer to Figure 16).
BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING
During acknowledge polling, the master first issues a START condition followed by a Slave Address Byte. The Slave Address Byte contains the X96012's Device Type Identifier and Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is busy within the high voltage cycle, then no ACK is returned. If the high voltage cycle is completed, an ACK is returned and the master can then proceed with a new Read or Write operation. Refer to Figure 17.
Byte Write Operation
In order to perform a Byte Write operation to the memory array, the Write Enable Latch (WEL) bit of the Control 6 Register must first be set to "1". See "WEL: Write Enable Latch (Volatile)" on page 12. For any Byte Write operation, the X96012 requires the Slave Address Byte, an Address Byte, and a Data Byte. See Figure 18. After each of them, the X96012 responds with an ACK. The master then terminates the transfer by generating a STOP condition. At this time, if all data bits are volatile, the X96012 is ready for the next read or write operation. If some bits are nonvolatile, the X96012 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X96012 does not respond to any requests from the master. The SDA output is at high impedance. A Byte Write operation can access bytes at locations 00h through FEh directly, when setting the Address Byte to 00h through FEh respectively. Setting the Address Byte to FFh accesses the byte at location 100h. The other sixteen bytes, at locations FFh and 101h through 10Fh can only be accessed using Page Write operations. The byte at location FFh can only be written using a "Page Write" operation. Writing to Control bytes which are located at byte addresses 80h through 8Fh is a special case described in "Writing to Control Registers" on page 20.
ISSUE START
ISSUE SLAVE ADDRESS BYTE (READ OR WRITE)
ISSUE STOP
NO ACK RETURNED?
YES
HIGH VOLTAGE COMPLETE. CONTINUE COMMAND SEQUENCE.
NO
Page Write Operation
ISSUE STOP
YES CONTINUE NORMAL READ OR WRITE COMMAND SEQUENCE
PROCEED
The 2176-bit memory array is physically realized as one contiguous array, organized as 17 pages of 16 bytes each. A "Page Write" operation can be performed to any of the GPM or LUT pages. In order to perform a Page Write operation to the memory array, the Write Enable Latch (WEL) bit in Control register 6 must first be set See "WEL: Write Enable Latch (Volatile)" on page 12. A Page Write operation is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 16 bytes (see Figure 19). After the receipt of each byte, the X96012 responds with an ACK, and the internal byte address counter is incremented by one. The page address remains constant. When the counter reaches the end of the page, it "rolls over" and goes back to the first byte of the same page.
FIGURE 17. ACKNOWLEDGE POLLING SEQUENCE
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly issued (including the final STOP condition), the X96012 initiates an internal high voltage write cycle. This cycle typically requires 5ms. During this time, any Read or Write command is ignored by the X96012. Write Acknowledge Polling is used to determine whether a high voltage write cycle is completed.
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X96012
WRITE SIGNALS FROM THE MASTER S T A R T SLAVE ADDRESS ADDRESS BYTE DATA BYTE S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
10 10
0 A C K A C K A C K
FIGURE 18. BYTE WRITE SEQUENCE
WRITE SIGNALS FROM THE MASTER S T A R T
2 < n < 16 ADDRESS BYTE S T O P
SLAVE ADDRESS
DATA BYTE (1)
DATA BYTE (N)
SIGNAL AT SDA 10 10 SIGNALS FROM THE SLAVE 0 A C K A C K A C K A C K
FIGURE 19. PAGE WRITE OPERATION
7 BYTES
5 BYTES 5 BYTES
ADDRESS = 0
ADDRESS = 6
ADDRESS = 11 ADDRESS = 7 ADDRESS POINTER ENDS UP HERE ADDRESS = 15
FIGURE 20. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11
For example, if the master writes 12 bytes to a 16-byte page starting at location 11 (decimal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6 within that page. Afterwards, the address counter would point to location 7. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. See Figure 20. The master terminates the loading of Data Bytes by issuing a STOP condition, which initiates the nonvolatile write cycle. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. A Page Write operation cannot be performed on the page at locations 80h through 8Fh. The next section describes the special cases within that page.
A Page Write operation starting with byte address FFh, accesses the page between locations 100h and 10Fh. The first data byte of such operation is written to location 100h.
Writing to Control Registers
The byte at location 80h, 85h, and 86h are written using Byte Write operations. They cannot be written using a Page Write operation. Control bytes 1 through 4, at locations 81h through 84h respectively, are written during a single operation (see Figure 21). The sequence must be: a START, followed by a Slave Address byte, with the R/W bit equal to "0", followed by 81h as the Address Byte, and then followed by exactly four Data Bytes, and a STOP condition. The first data byte is written to location 81h, the second to 82h, the third to 83h, and the last one to 84h.
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FN8216.3 February 20, 2008
X96012
The four registers Control 1 through 4, have a nonvolatile and a volatile cell for each bit. At power-up, the content of the nonvolatile cells is automatically recalled and written to the volatile cells. The content of the volatile cells controls the X96012's functionality. If bit NV1234 in the Control 0 register is set to "1", a Write operation to these registers writes to both the volatile and nonvolatile cells. If bit NV1234 in the Control 0 register is set to "0", a Write operation to these registers only writes to the volatile cells. In both cases the newly written values effectively control the X96012, but in the second case, those values are lost when the part is powered down. If bit NV1234 is set to "0", a Byte Write operation to Control registers 0 or 5 causes the value in the nonvolatile cells of Control registers 1 through 4 to be recalled into their corresponding volatile cells, as during power-up. This doesn't happen when the WP pin is LOW, because Write Protection is enabled. It is generally recommended to configure Control registers 0 and 5 before writing to Control registers 1 through 4. When reading any of the control registers 1, 2, 3, or 4, the Data Bytes are always the content of the corresponding nonvolatile cells, even if bit NV1234 is "0". See "Control and Status Registers" on page 9.
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (see Figure 22). The master initiates the operation issuing the following sequence: a START, the Slave Address byte with the R/W bit set to "0", an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to "1". After each of the three bytes, the X96012 responds with an ACK. Then the X96012 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte. See Figure 22. The Data Bytes are from the memory location indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 10Fh the pointer "rolls over" to 00h, and the device continues to output data for each ACK received. A Read operation internal pointer can start at any memory location from 00h through FEh, when the Address Byte is 00h through FEh respectively. But it starts at location 100h if the Address Byte is FFh. When reading any of the control registers 1, 2, 3, or 4, the Data Bytes are always the content of the corresponding nonvolatile cells, even if bit NV1234 is "0". See "Control and Status Registers" on page 9.
FOUR DATA BYTES
SIGNALS FROM THE MASTER
S T A R T
WRITE SLAVE ADDRESS ADDRESS BYTE = 81h DATA BYTE FOR CONTROL 1 DATA BYTE FOR CONTROL 4 S T O P
SIGNAL AT SDA 10 10 SIGNALS FROM THE SLAVE 0 A C K 10 00 0 0 01 A C K A C K A C K
FIGURE 21. WRITING TO CONTROL REGISTERS 1, 2, 3 AND 4
SIGNALS FROM THE MASTER
S T A R T
SLAVE ADDRESS WITH R/W = 0
ADDRESS BYTE
S T A R T
SLAVE ADDRESS WITH R/W = 1
A C K
A C K
S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
10 10
0 A C K A C K
10 10
1 A C K
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 22. READ SEQUENCE
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FN8216.3 February 20, 2008
X96012
Data Protection
There are four levels of data protection designed into the X96012: 1- Any Write to the device first requires setting of the WEL bit in Control 6 register; 2- The Block Lock can prevent Writes to certain regions of memory; 3- The Write Protection pin disables any writing to the X96012; 4- The proper clock count, data bit sequence, and STOP condition is required in order to start a nonvolatile write cycle, otherwise the X96012 ignores the Write operation.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (LOW), any Write operations to the X96012 is disabled, except the writing of the WEL bit.
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FN8216.3 February 20, 2008
X96012 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 23
FN8216.3 February 20, 2008

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